Seed II Funding in Progress

3D Chips
with 2D Materials

Ease on Three-dimensional Memory & Logic Solutions. FS2 pioneers atomic-scale 2D semiconductor technology for low energy-consumption, cost, and latency computing.

Explore Technology Investment Inquiry
Absolute
Cost Efficiency Maximized
Maximize
Energy Saving Potential
<400°C
Low-Temp Process
12"
Wafer Scale
M3D Chip Architecture
M3D 3D Chip Architecture
01

2D Material Layer

Wafer-scale MoS2, WSe2 growth

02

Monolithic Integration

3D sequential integration technology

03

<400°C Low-Temp

Thermal budget management for BEOL

About FS2

The Post-Silicon Era Starts Here

The faster compute, more energy dilemma. AI needs efficiency—global data center power consumption will reach 945 TWh by 2030. Silicon alone cannot keep up beyond 2030.

FS2 develops "atomic" 2D semiconductors (WSe₂, MoS₂) that enable monolithic 3D integration at just <400°C—compatible with legacy IC infrastructure.

Single Crystal 2D on Any Surface
Wafer-Scale Process
Plug-and-Play with Si Fabs
Multi-Tier M3D Integration
Core Tech
Atomic-layer MOCVD Growth
IP Portfolio
Multiple 3D Stacking Patents
The Problem

AI Is Hitting a Wall.
We're Breaking Through It.

As AI models grow exponentially, the gap between compute speed and memory bandwidth widens every year. This is the Memory Wall — and it's becoming the defining bottleneck of the AI era.

The Bottleneck

AI models are scaling 240× every two years.
Memory bandwidth is not keeping up.

LLMs evolve far faster than hardware — the gap is widening, not closing

Data moves constantly between distant memory and logic, draining power

Silicon alone cannot solve this — a fundamentally new architecture is needed

FS2's Answer

Stack memory directly on logic.
Eliminate the gap entirely.

Monolithic 3D integration places memory and logic in a single chip stack

Ultra-short interconnects mean near-zero latency and a fraction of the power cost

2D materials enable this stacking at low temperature — compatible with existing fabs

FS2 is building the technology to break the Memory Wall — enabling the next generation of AI chips that are faster, denser, and radically more efficient.

Technology

World's First Single-Crystal 2D on Amorphous Films

Breaking the thermal barrier with low-temperature growth ready for monolithic integration.

01

2D Material Layer

Wafer-scale MoS2, WSe2 growth

02

Monolithic Integration

3D sequential integration technology

03

<400°C Low-Temp

Thermal budget management for BEOL

FS2 Technology in Action
FS2 Tech Solution - 2D Direct Growth and Monolithic 3D
1
Geometric Confinement Growth Patterned 2D semiconductor array on amorphous substrate — wafer-scale, uniform, single-crystal
2
Single Crystal 2D Patterns World-first single-crystalline TMD grown below 400°C, enabling direct monolithic stacking
3
Multi-tier M3D Integration 1000× shorter interconnect via monolithic 3D — via pitch H < 0.1μm, D < 50nm
Exceptional
Thermal Stability & Reliability
Maximum
Energy Efficiency for AI Workloads
Superior
Carrier Mobility & Transconductance
Team

The Right Team for the Hardest Problems

World-class experts in 2D materials, semiconductor physics, and deep-tech commercialization.

Jekyung Kim
Leadership

Jekyung Kim

Co-CEO & Co-Founder

KAIST Ph.D. · Led FEOL Process Dev. for GAA 3nm Node · 10 yrs semiconductor

Sang-Hoon Bae
Leadership

Sang-Hoon Bae

Co-CEO & Co-Founder

UCLA Ph.D. · ~100 papers (Nature, Science) · Citation >10,000 · >10 yrs semiconductor

Intak Jeon
Operations

Intak Jeon

COO

MIT Ph.D. · Chip Integration & Memory Dev. · 4× Samsung Best Paper Award · >6 yrs Memory

Chankeun Park
Research

Chankeun Park

Director of R&D

UV LED Commercialization · LG Innotek Inventor Award · LG Best Product Award · >10 yrs MOCVD

Bo-In Park
Engineering

Bo-In Park

Director of Engineering

KAIST Ph.D. · 2.5D Chip Process Dev. (BEOL, TSV) · >10 yrs semiconductor

Yeji Park
Process Engineering

Yeji Park

Process Engineer

Korea Univ. M.S. · Materials Sci. & Eng. · 5 yrs semiconductor & research

Hyeonuk Jung
Process Engineering

Hyeonuk Jung

Process Engineer

Kyung Hee Univ. B.S. · Materials Sci. & Eng.

Advisory Board
Sungkyu Lim
Advisory Board

Sungkyu Lim

Advisor

Professor (USC) · DARPA Program Manager · 3D Integration Expert

Jeehwan Kim
Advisory Board

Jeehwan Kim

Advisor

Assoc. Professor (MIT) · IBM Master Inventor · Device Expert · Key Technique Inventor

Kyusang Lee
Advisory Board

Kyusang Lee

Advisor

Assoc. Professor (UVA) · Circuit Expert

Investment & Markets

Building the Future of Semiconductors

$1.6T
Semiconductor Market 2030
3 VCs
Seed I Investors + Grants
8"→12"
Commercialization Roadmap
Contact

Build the Future with Us

For those daring to innovate. Join us in pioneering the next generation of semiconductor technology.

💼

Investment

Seed II funding
in progress

🤝

Partnership

Equipment & process
innovation

👥

Careers

Join world-class
experts

[email protected]